The technology of integrated circuits has developed rapidly. Along with the increase in scale of circuits, the faster the speed. Meanwhile, the number of gate count in the circuits increases accordingly. The integrated circuits require a more reliable power supply to ensure normal function. The expansion of circuit scale requires more and more transistors, which are usually realized in stack configurations to effectively control the area of the chip. Thus, how to supply power to these transistors becomes a crucial question. Normally, there are two kinds of power supply according to different packaging methods: one is called “topside power supply” mostly used in flip-chip packages; the other is called “lateral power supply” (used for wire-bonding). Topside power supply is more advantageous than the lateral power supply.
Electrical elements' connection in the integrate circuits are configured in stacks together to effectively control chip area. Thus, such structure presents certain difficulties in terms of power supply. In order to address the problems with power supply of a chip in the flip-chip packaging, power/ground (P/G) network provide power supply to all transistors. More specifically, power lines and ground lines of the standard cells with a wide range of functionalities are respectively connected to power stripes and ground stripes in the P/G network, which is then connected to an external power supply, thereby realizing power delivery.
It should be noted here that since the present invention is mainly directed to improvement of P/G network, thus hereinafter, circuit cells regardless of their functionalities are simplified as circuit cells with a power line and a ground line, referred to as “standard cells”. Meanwhile, all the standard cells have the same height, while the widths of the cells may vary. Additionally, this uniform height of the standard cells is referred to as “standard height”.
In current large-scale circuit designs where the size and speed of the circuits increase relentlessly, although multi-layers of metal are used, resources for interconnections (i.e. P/G network resources) are still relatively insufficient. In order to get more interconnection resources, the chip area is forced to enlarge. However, this brings problems such as increased cost, timing and IR drop.
Current P/G network designs for large-scale circuit do not take the sizes of the standard cells and their power/ground width into account, as described in FIG. 1A. FIG. 1A is a schematic diagram illustrating a layout of a P/G network. In the drawing, designations of “standard cells” are omitted, only their power lines Vdd and ground lines Vss are indicated. Additionally, it should be noted that the Vdd and Vss are spaced apart, and the space between them indicates the “standard height” for fitting a single “standard cell”. “Standard cells” are arranged back-to-back, such that two “standard cells” share the same Vdd or Vss. Other arrangements are possible to one skilled in the art, and appropriate modifications are made when applying the technical features of the present invention. The following descriptions of the present invention will be made with respect to this commonly seen arrangement as shown in FIG. 1A. Normally, the row direction of the standard cells is called the horizontal direction (It should be noted that “vertical” and “horizontal” directions refer to the layout directions, wherein the row direction of the standard cells is called the “horizontal” direction while the direction perpendicular to it is called the “vertical” direction). Typically, a metal stripe in the horizontal direction is located at a higher layer while a metal stripe in the vertical direction is located at a lower layer. Referring still to FIG. 1A, in current technique, the width of the metal stripes is not carefully calculated, so it is often larger than twice of the standard height. As a result, the width of a single metal stripe may cover standard cell's power line Vdd and ground line Vss simultaneously. Thus, metalstripes n layers higher than that the layer on which the power lines Vdd and ground lines Vss of the standard cells reside are used as vertical metal lines 101P and 101G; while metalstripes n+1 layers higher are used as horizontal metal lines 102P and 102G. in the P/G (power/ground) network. (FIG. 1A is viewed from a bottom-up perspective, so Vdd and Vss are seen first and the vertical metal lines 101P and 101G and the horizontal metal lines 102P and 102G are partially blocked). The reason for doing this is that the power lines Vdd or ground lines Vss of all the standard cells can all be connected to the vertical metal stripes of P/G network. As shown in FIG. 1A, Vdd and Vss connect to 101G and 101P respectively through Vias 100. Since the power lines Vdd and the ground lines Vss of the standard cells are horizontally arranged, they connect to the metal stripes of P/G network in the vertical direction, without causing P/G short. The metal stripes of P/G network in the vertical direction must be lower-layer metals, while the metal stripes of P/G network in the horizontal direction is higher-layer metals.
If the higher-layer metals are vertical and the lower-layer metals are horizontal, then metalstripes of P/G network n layer higher than that of the power lines Vdd or ground lines Vss of the standard cells are used as the horizontal metalstripes, while the metalstripes of P/G network n+1 layer higher are used as the vertical metal stripes, as shown in FIG. 1B. In this case, part of the power lines Vdd or ground lines Vss of the standard cells are prevented from connecting to the vertical P/G network at the higher layer (n+1) by the horizontal P/G network at the lower layer (n), causing IR drop and other problems. Referring to FIG. 1B (similarly viewed from a bottom-up perspective), metal stripes of P/G network 103P and 103G n+1 layer higher than the power lines Vdd or ground lines Vss of the standard cells are vertical while metal stripes 104P and 104G n layer higher than the power lines Vdd or ground lines Vss of the standard cells are horizontal. In this case, such as the location indicated by block 105, the power lines Vdd or ground lines Vss of the standard cells cannot connect to the higher-layer metal stripes 103P or 103G since they are blocked by the lower-layer metal stripes 104P and 104G, causing IR drop and other problems. In view of this, if in the current design, a chip employs 2n-layer metal fabrication technique as well as flip-chip packaging, then metals at the (2n−1)th layer are designed as P/G network in the horizontal direction, while metals at the (2n−2)th layer and the (2n)th layer stacked on top of that are used as power and ground stripes in the vertical direction, i.e. there are two layers of vertical P/G lines. This would eliminate the problem of overlapping as shown in FIG. 1B. However, it would take up too much layout resources.
From the above, it can be seen that one main reason for inefficient usage of layout resources and high cost is the unreasonable design of the P/G networks, wherein components are not elaborately arranged and the resources are unreasonable deployed. Therefore, there is a need for a more reasonable P/G network arrangement in order to accommodate the requirements in chip designs.